News

October 2011: the european project SMAC starts and EDALab is one of the partners. The kick-off meeting is scheduled in Catania (IT) the 18th of October.

September 2011: EDALab presents the eCos embedded OS on ARM platform the next 28 September at the event organized by Atmel and MSC, in cooperation with Metodo 2

September 2011: HIFSuite and radCHECK discussed during the Panel on "Assertions Propagation, Refinement and Reuse across Abstraction Levels and Description Languages" FDL'11
June 2011: EDALab will present with STM Products radCHECK and HIFSuite at the Design Automation Conference 2011 in San Diego (CA). Our booth number in the exhibition area is 1920. Come and visit us !
Hardware modelling
Print E-mail

Escape from the Design and Verification Babel

Technological advances in the production of integrated circuits require new tools and design techniques to face large-scale projects and optimization in a context in which the boundary between hardware and software is weak thus opening new opportunities. The ideas of the Electronic System Design (ESD) research group are implemented in EDALab's products.

 

HIFSuite

A suite of libraries and tools to manipulate hardware models written in SystemC, Verilog and VHDL. See specific site for further information.

radCHECK

Extension of the radCASE tool for the design of embedded software. radCHECK allows to specify and verify properties about embedded software. This tool is distributed by STM Products; further details are provided on http://www.verificationsuite.com

SCNSL

Library based on SystemC for the simulation of packet-based networks (e.g., Internet, ethernet, WLAN, filedbus, Zigbee). The library is available as open source project on SourceForge.

HSN

Tool for the simulation of complex systems; it relies on different simulators, each specific for the aspect to be simulated, i.e., hardware components (H), software modules (S), network elements (N).

 
Site map