Digital Modeling and Verification
The continuous enhancements in the silicon market requires new tools and design techniques to face problems and large-scale optimizations. The research ideas of the ESD Group are engineered by EDALab tools, which open new ways to hardware/software codesign and thus lead to new business opportunities.
EDALab has developed HIFSuite, a set of tools and libraries that ease the design of embedded systems in VHDL, Verilog and SystemC.
| HIFSuite |
A suite of libraries and tools to manipulate hardware models written in SystemC, Verilog and VHDL. See specific site for further information.
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| SCNSL |
SystemC library for packet-based network modeling available for download at SourceForge.
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| HSN |
HSN is a design tool that helps the designer to develop applications without having the real hardware in the hand, because it allows to simulate all the parts of the real system: the hardware, the software and the network.
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EDALab has the ability to create SystemC models of NES based on:
- SystemC models obtained by automatic translation with HIFSuite of VHDL and Verilog modules
- SystemC models at TLM level created from scratch or automatically generated with HIFSuite by abstraction from the corresponding RTL model
- Network and bus Models based on SCNSL
- CPU models for the execution of embedded SW based on Qemu and linked to SystemC models by HSN
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